As telecommunications networks are increasingly moving from time division multiplexing (TDM) based protocols such as Synchronous Optical Networking (SONET) to packet switching technologies, maintaining network wide synchronization of nodes has become more challenging. A related challenge is network planning of synchronization topology. This is especially important when integrating TDM networks with packet switching network elements having T1 and E1 interfaces. Unlike TDM connections, packet-switched networks are not designed for network-wide synchronization of nodes. Techniques have been developed to extract timing and synchronization information from the packet data stream, generally referred to as timing-over-packet. Thus, although timing-over-packet systems can exchange timing information using packets, the inherent characteristics of the packet-switched network affect the accuracy and reliability of the synchronization. For example, unlike circuit-switched networks, packet-switched networks use variable paths with a variable bit rate, such that timing packets may arrive at nodes at varying intervals or may not arrive at all, thereby affecting the synchronization of the nodes.
Synchronization protocols such as Synchronization Status Messaging (SSM) allow for maintaining the network synchronization using a hierarchical network clocking structure of a master or primary clock such as a Stratum 1 reference and slave or secondary clocks such as Stratum 2 or Stratum 3. SSM provides for selection of the best reference to be used at each network element. SSM provides a minimal level of timing loop avoidance to ensure two adjacent network elements do not time off each other, but it does not ensure avoidance of loops involving three or more network elements. Routers and other packet switching network elements are increasingly used to provide network synchronization using timing-over-packet or synchronous Ethernet techniques. Currently SSM is not yet universal for packet switching network elements; not all telecommunication packet switching network elements support SSM. Routers may not have sufficient network intelligence to initiate automatic clock reconfiguration based on network failures.
Currently, planning of sync clock topology for timing-over-packet networks to ensure synchronization performance is becoming increasingly challenging. Typically, in order to measure sync clock performance in a timing-over-packet network, external test equipment is required to measure the timing performance and actual connections in the network need to be broken or disabled in order to measure the effect of network failures on the performance of the timing-over-packet network sync clock performance of the network. Therefore improvements in tools for planning and simulating sync clock performance for timing-over-packet networks is desired.